Internet traffic has and is expected to further grow exponentially along Moore's law. Consequently, network line speed has doubled about every two years in the past. However, integrated circuit and memory clock rates have not improved to the same extent, one reason being that on-chip wire delays between device logic do not scale with the ratio of geometry sizes but rather stay constant. A common solution to address this issue of interconnect delays in high-speed design is a parallelization of resources, such as parallel memory banks of traffic managers or a high-number of comparatively low-speed chip-to-chip interfaces.
Such a parallelization of resources for high-speed data packet processing comes at the expense of required space and power consumption, and ultimately, higher costs. Furthermore, the increased power consumption combined with the increasingly smaller hardware design of today's computers and packet-processing network devices results in high power densities. These high power densities impair chip reliability and life expectancy, increase cooling costs, and, for large data centers, even raise environmental concerns.
In state-of-the-art designs, two forms of power consumption, dynamic power consumption and static power consumption, can be reduced by circuit and logic level techniques (e.g. transistor design, low-power interconnects), caching architectures (e.g. adaptive caches), and dynamic voltage scaling (DVS).
However, the majority of these techniques are too complex for high-speed, i.e., 100 Gb/s and above, packet processing devices, such as network processors (NPs), traffic managers (TMs) and switch fabrics (SFs). For example, the DVS method, which modulates the chip's clock frequency and supply voltage, is very hard to incorporate in high-speed packet processing devices which have special requirement for bandwidth, processing latency and jitter.